Historically, printed-circuit-board testing was accomplished using bed-of-nails in-circuit test equipment. However, the development of fine-pitch, high-count VLSI circuits (e.g. application specific integrated circuits) has encouraged the industry to develop test and fault detection protocols which do not require direct observability of locations within the circuitry as, for example, through the use test points and pins. The problem is further complicated by the advent of deep sub-micron technology (i.e. channel lengths no greater than about 0.5 microns) wherein faults are not only consistent with an open/short circuit fault model, but may also include faults characterized by a parasitic model, e.g., slow transitions and paths caused by, for example, particle random defects in the gate oxide, the inner-dielectric layers, or the interconnecting plugs and vias. These areas are especially vulnerable due to the geometry density and processing steps required to create them, such as chemical/mechanical planarization.
While the problems are mitigated through the use of design-for-manufacturability techniques (i.e. metal/via density), faults and defects are not entirely eliminated. Even when using redundant via interconnects, one or more of the vias could be open or incomplete thus changing the resistivity through the interconnect. Furthermore, gate oxide defects can cause degradation in a transistor's turn-on/turn-off time thus impacting overall transition time which, in turn, could damage the device and create additional performance and/or reliability problems.
The above described defect mechanisms induce parametric variations, and the best method for detecting such variations is through time analysis and production time tests. The timing induced variations are most applicable to combinatorial logic and can be screened through timing thresholds by means of either frequency functional tests or delayed fault modeling. Unfortunately, partial testing at different frequencies is globally incomplete and does not detect all internal delay-induced defects. Alternatively, additional circuitry could be provided which permits individual clock-time control.
One known solution involves the use of sequential storage elements which provides virtual access around (i.e. a sequential storage element) or within (i.e. an internal sequential storage element) circuitry by applying a stream of test vectors each comprised of serial patterns of ones and zeros to the integrated circuit device or portions thereof by means of, for example, one or more on-board shift registers deployed between blocks of combinatorial logic. The test pattern is shifted into the shift register and then into the logic circuitry to initialize the test paths of the logic circuitry, and the response data is captured to detect faults. During standard operations, the sequential storage elements remain inactive and allow data to propagate through the logic circuitry normally. However, during a test mode, the test pattern signals are preloaded into the shift register flip-flops, applied to the inputs of the logic elements for testing down-stream logic devices, and presented to the capture mechanism.
Obviously, to be effective, the time at which the scan pattern signals are applied to the logic inputs must be precisely determinable in order to accurately calculate the transition times and propagation delays of the individual logic elements and paths. For example, if two or more logical ones are shifted through adjacent bits of the shift register, a logical 1 may be applied to the input of the capture mechanism for more than one successive clock period. An increase in the path resistance manifested as increased delay might not be detected because the signal being captured by the capture mechanism may have commenced as a result of a previously shifted level.
One solution to this problem is provided in Bedal et al., U.S. Patent Application Publication No. 2003/0149924, entitled “Method and Apparatus for Detecting Faults on Integrated Circuits,” published Aug. 7, 2003, which is hereby incorporated by reference. In the mechanism described in Bedal et al, a sequential storage element is provided for use in a device for testing integrated circuits. The sequential storage element includes a multiplexer and a switching device. The multiplexer provides a first signal to the switching device when the control signal is in a first state and a test signal to the switching device when the control signal is in a second state.
In a test operation, a scan pattern is stored in a first plurality of input sequential storage elements configured as described above. This scan pattern is then presented to the logic circuit when the control signal is in the first state. The scan pattern is inverted when the control signal transitions from its first state to its second state to create a measuring edge. The output of the logic circuit is then captured in a plurality of output sequential storage elements and the delay between the measuring edge and the capture is measured to determine propagation delay.
This type of testing is referred to as a static test because the input signal is sent as a minimum on a previous clock pulse but may also have been available several clock pulses prior. These static tests offer a proven structured approach to static faults. However, it cannot be determined whether each path through the combinational logic of the integrated circuit is operating within their acceptable delay range. Therefore, it would be desirable to have a method and apparatus that permits isolation of individual paths within an integrated circuit so that timing delay along the path may be accurately tested.